Als ik het goed heb is die Errata 123 voor RevE cpu's, en zorgt ervoor dat een bepaalde bug wordt omzeilt. Ik moet hem aan laten staan met m'n rev-E4 SanDiego die de bug dus wel heeft.
Maar een aantal Dual Core procs hebben hem weer niet.
Met m'n rev-E6 Opteron 146 kon ik Errata 123 weer uitzetten.
Op default check je bios de cpu string en als deze de aangeeft dat de desbetreffende proc de bug heeft, dan zet je bios de omzeiling zelf aan
Nog even opgezocht, alleen houden ze geen rekening met de verschillen in de E3/E4/E6 revisies:
Errata 94
Errata 94 refers to the 94th bug identified in AMD Athlon and Opteron processors. This bug affects the sequential prefetch feature in those processors.
When there's an instruction cache miss, the sequential prefetch mechanism in affected processors may incorrectly prefetch the next sequential cache line. This may cause the processor to hang. Affected 64-bit processors that run 32-bit applications may end up executing incorrect code.
This bug affects the following processor families :
AMD Opteron (Socket 940)
AMD Athlon 64 (Socket 754, 939)
AMD Athlon 64 FX (Socket 940, 939)
Mobile AMD Athlon 64 (Socket 754)
AMD Sempron (Socket 754, 939)
Mobile AMD Sempron (Socket 754)
Mobile AMD Athlon XP-M (Socket 754)
When enabled, the BIOS will disable the processor's sequential prefetch mechanism for any software that operates in Long Mode.
When disabled, the BIOS will not disable the processor's sequential prefetch mechanism. This improves its performance.
When set to Auto, the BIOS will query the processor to see if it is affected by the bug. If the processor is affected, the BIOS will enable this BIOS feature. Otherwise, it will leave it disabled.
Errata 123
Errata 123 refers to the 123rd bug identified in AMD Athlon and Opteron processors. This bug affects the cache bypass feature in those processors.
These processors have an internal data path that allows the processor to bypass the L2 cache and initiate an early DRAM read for certain cache line fill requests, even before receiving the hit/miss status from the L2 cache.
However, at low core frequencies, the DRAM data read may reach the processor core before it is ready. This causes data corruption and/or the processor to hang.
This bug affects the following processor families :
Dual Core AMD Opteron (Socket 940, 939)
AMD Athlon 64 X2 (Socket 939)
This BIOS feature is a workaround for the bug. It allows you to disable the cache bypass feature and avoid the bug from manifesting.
When enabled, the processor will not bypass the L2 cache to prefetch data from the system memory.
When disabled, the processor will continue to bypass the L2 cache for certain cache line fill requests. This improves its performance.
When set to Auto, the BIOS will query the processor to see if it is affected by the bug. If the processor is affected, the BIOS will enable this BIOS feature. Otherwise, it will leave it disabled.
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Voor 76% gewijzigd door
Demon_Eyez op 30-05-2006 16:53
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