Geheugen 133 ?

[Dezjay]

SPD dump of Dimm in socket :0

SPD - Number of bytes available :128 bytes
SPD - Total bytes of memory device :256 bytes
SPD - Revision :1,2
SPD - Checksum :OK

Manufacturer - Name :Unknown ID: 0000000000000000
Manufacturer - Location :0 ($00)
Manufacturer - Part Number :
Manufacturer - Revision code :00 ($0000)
Manufacturer - Manufacturing date :$0062
Manufacturer - Assembly Serial Number :0000
Manufacturer - Manufacturer Specific Data :

Memory - Type :Sync Dram
Memory - Row Addresses :0 | 12
Memory - Column Addresses :0 | 8
Memory - Module Banks :2
Memory - Data Width :64
Memory - Voltage interface standard :LVTTL
Memory - Cycle time at Max. Supported CAS :10.0 ns.
Memory - SDRAM Access from Clock at :6.0 ns.
Memory - DIMM Configuration type :None
Memory - Refresh Rate/Type :Self Refresh, Normal (15.625 us)
Memory - Minimum Clock Delay :1
Memory - Burst Lengths Supported :Page 1 2 4 8
Memory - Banks on Each SDRAM device :4
Memory - CAS Latencies Supported :3
Memory - CS Latencies Supported :0
Memory - WE Latencies Supported :0
Memory - Min. Clock Cycle Time @ CL X-1 :0.0 ns.
Memory - Max. Data Access Time from Clock @ CL X-1 :0.0 ns.
Memory - Min. Clock Cycle Time @ CL X-2 :0.0 ns.
Memory - Max. Data Access Time from Clock @ CL X-2 :0.0 ns.
Memory - Minimum Row Precharge Time :20 ns.
Memory - Minimum Row Active to Row Active delay :20 ns.
Memory - Minimum RAS to CAS delay :20 ns.
Memory - Minimum RAS Pulse Width :50 ns.
Memory - Module Bank Density :32 MB.
Memory - Module Total Density :64 MB.
Memory - Speed :100 Mhz


SPD dump of Dimm in socket :1

SPD - Number of bytes available :128 bytes
SPD - Total bytes of memory device :256 bytes
SPD - Revision :1,2
SPD - Checksum :OK

Manufacturer - Name :Unknown ID: 0000000000000000
Manufacturer - Location :0 ($00)
Manufacturer - Part Number :
Manufacturer - Revision code :00 ($0000)
Manufacturer - Manufacturing date :$0000
Manufacturer - Assembly Serial Number :0000
Manufacturer - Manufacturer Specific Data :

Memory - Type :Sync Dram
Memory - Row Addresses :0 | 12
Memory - Column Addresses :0 | 9
Memory - Module Banks :2
Memory - Data Width :64
Memory - Voltage interface standard :LVTTL
Memory - Cycle time at Max. Supported CAS :10.0 ns.
Memory - SDRAM Access from Clock at :6.0 ns.
Memory - DIMM Configuration type :None
Memory - Refresh Rate/Type :Self Refresh, Normal (15.625 us)
Memory - Minimum Clock Delay :1
Memory - Burst Lengths Supported :1 2 4
Memory - Banks on Each SDRAM device :4
Memory - CAS Latencies Supported :2 3
Memory - CS Latencies Supported :0
Memory - WE Latencies Supported :0
Memory - Min. Clock Cycle Time @ CL X-1 :10.0 ns.
Memory - Max. Data Access Time from Clock @ CL X-1 :6.0 ns.
Memory - Min. Clock Cycle Time @ CL X-2 :0.0 ns.
Memory - Max. Data Access Time from Clock @ CL X-2 :0.0 ns.
Memory - Minimum Row Precharge Time :20 ns.
Memory - Minimum Row Active to Row Active delay :20 ns.
Memory - Minimum RAS to CAS delay :20 ns.
Memory - Minimum RAS Pulse Width :50 ns.
Memory - Module Bank Density :64 MB.
Memory - Module Total Density :128 MB.
Memory - Speed :100 Mhz

Dit zegt ie ken het op 133 Mhz ? rekken

(kweet dat dit al eens langs is gekomen maar ik kan het niet vinden

[Verwijderd]

Hmm... Die tweede gaat wellicht nog lukken op CAS 3, maar die eerste ondersteunt alleen CAS 3 op 100 MHz. Dat gaat-ie dus niet leuk vinden...
Maar ik heb ooit 's gelezen dat CAS 2 + 100 MHz beter is dan CAS 3 + 133 MHz, maar weet niet precies meer waarom dat was... Iemand?

[Dezjay]

Gaat me alleen om die 133 Mhz

[Verwijderd]

Ja, dat begrijp ik...

Maar: 100 MHz CAS 2 kun je op 133 MHz CAS 3 laten lopen. 100 MHz CAS 3 kun je i.h.a. niet op 100 MHz CAS 3 laten lopen.

CAS 2 is beter dan CAS 3, dat zijn nl. het aantal waitstates, hoe lang het geheugen wacht voordat-ie weer wat nieuws kan doen (of zo)

[Verwijderd]

gewoon proberen toch...