[ASSEMBLER Z80] wat moet je met Register R?

[Gabriel-LG]

Ik ben net begonnen met assembler voor de MSX (een zilog Z80 computer). In het boek dat ik erbij heb wordt o.a. een register R (=refresh) beschreven. Dit register kan ik niet helemaal vatten wat het doet.

Register R (refresh = opfrissen)

De computer gebruikt dit register als teller om regelmatig de inhoud van het dynamische geheugen op te frissen. Door in korte tijd dezelfde geheugeninhoud steeds opnieuw te laden wordt voorkomen dat informatie verloren gaat.

Dit is eigelijk het enige register dat ik niet kan vatten
(wees maar niet bang, ik ben nog wel een beetje n00b in assembler, maar ik ben niet van plan jullie de oren van het hoofd te vragen )

[Pooh]

About the R register:

This is not really an undocumented feature, although I have never seen any thorough description of it anywhere. The R register is a counter that is updated every instruction, where DD, FD, ED and CB are to be regarded as separate instructions. So shifted instruction will increase R by two. There's an interesting exception: doubly-shifted opcodes, the DDCB and FDCB ones, increase R by two too. LDI increases R by two, LDIR increases it by 2 times BC, as does LDDR etcetera. The sequence LD R,A/LD A,R increases A by two, except for the highest bit: this bit of the R register is never changed. This is because in the old days everyone used 16 Kbit chips. Inside the chip the bits where grouped in a 128x128 matrix, needing a 7 bit refresh cycle. Therefore ZiLOG decided to count only the lowest 7 bits. You can easily check that the R register is really crucial to memory refresh. Assemble this program:
ORG 32768
DI
LD B,0
L1: XOR A
LD R,A
DEC HL
LD A,H
OR L
JR NZ,L1
DJNZ L1
EI
RET

It will take about three minutes to run. Look at the upper 32K of memory, for instance the UDG graphics. It will have faded. Only the first few bytes of each 256 byte block will still contain zeros, because they were refreshed during the execution of the loop. The ULA took care of the refreshing of the lower 16K (This example won't work on the emulator, of course!).

linkje: http://www.geocities.com/SiliconValley/Peaks/3938/z80info.htm

of nog duidelijker:

The Z-80 CPU contains a memory refresh counter to enable dynamic memories
to be used with the same ease as static memories. Seven bits of this 8 bit
register are automatically incremented after each instruction fetch.
The eight bits will remain as programmed with the LD R,A instruction.
The data in the refresh counter is sent out on the lower portion of the
address bus along with a refresh control signal while the CPU is decoding
and executing the instruction. The programmer can load the R register for
testing purposes, but this register is normally NOT used by the programmer.
During refresh, the contents of the I register are placed on the upper
8 bits of the address bus.

en linkje: http://www.classicgaming.com/epr/processo/z80_faq2.htm

Het belangrijkste punt is dus dat de geheugenchips 'vergeten' wat erin staat, tenzij ze elke keer een refresh krijgen. Tegenwoordig regelt een geheugencontroller zoiets, op de Z80 moet je dat blijkbaar zelf (met de processor) regelen.