Op vrijdag 02 november 2001 11:08 schreef Citect het volgende:
Wat wil dat in feite zeggen delay read latch?
Dit is een duidelijke uitleg denk ik:
DRAM read latch delay (VIA chipset only)
If the memory clock frequency is increased, the cycle time gets shorter. Therefore, the data valid window (tDV), that is the time during which the chipset can receive data from the DRAM would come earlier (on an absolute time scale) and could possibly expire before the data from the DIMMs arrive. In order to compensate, tDV needs to be delayed or moved further back on the cycle to synchronize with the data output holding time of the DIMMs. In the case of the KT chipset, the situation is a bit more complicated since the Athlon family uses what is called clock forwarding or clock syncronous transfer. That is, a reference signal synchronizes all devices. Keep in mind that the KT chipset is a variation of the KX chipset and based on the timing parameters of the original SlotA Athlon. The socketed Thunderbird has shorter traces and, therefore, is able to receive data earlier relative to the originally established timing characteristics. Therefore, for example, the ASUS A7V BIOS even features a negative DRAM read latch delay of 0.1ns, that is, the data valid window opens even before the reference signal arrives. With all DIMMs tested, though, the Auto setting worked as well as any other manual setting.
In feite is het dus een foutje dat is ontstaan door de overgang van de KX naar de KT chipset waarbij bepaalde settings zijn overgenomen zonder ze af te stemmen op de nieuwe setup.
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