Bank cycle time [5T, 7T] or [6T, 8T]
The bank cycle time (Tras) specifies the number of clock cycles needed after a bank active command before a precharge can occur. Trc specifies the minimum cycle time until the same bank can be reactivated. Since a precharge has a latency of 2 or 3 cycles, the Trc is the sum of Tras and RAS precharge time. The BIOS offers 5T,7T and 6T,8T, that is, 7 or 8 cycles bank cycle time.
Most current high-end SDRAM is specified at about 50 ns cycle time. In turn, this means that, theoretically, at up to 133 MHz (7.5ns clock cycle), it is possible to run at a Trc of 7T (7x7.5ns=52 ns). If the clock frequency is increased, the number of cycles has to be increased, too, in order to provide the 50 ns. In other words, the theoretical limitation of the memory speed is somewhere around 166 MHz (8x6ns = 48ns) since there are no additional clock cycles provided for in the current BIOS.
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SDRAM Page Closing Policy [One Bank] or [All Banks]
This entry is somewhat obscure. In general, the theory behind it is that, after a page miss, the page needs to be closed and precharged again. If the next set of data is in another bank, this bank would be already be precharged and ready to receive the address. In other words, issuing of a Close All Banks command, will increase the penalty for data access in the main memory.
In a situation where the integrated graphics are relying on the united memory architecture, the situation is quite different, though. Graphics data are usually very large and if a miss occurs, it may be better to close all banks and precharge them afterwards again, just to be ready. A single bank closing command would not add any performance in this case.
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