SPI continious clock

[roel0]

Ik ben bezig met een driver te schrijven voor SPI op een baremetal board (frdm-k64f). Ik heb momenteel enkel nog maar de initialisatie geschreven. Ik had deze al graag getest met mijn osciloscoop, daarom heb ik de bit in het Continious Clock register aan gezet. Echter er verschijnt geen clock. Betekent Continious Clock niet wat ik denk dat het betekent?

code:

int frdm_spi_init(SPI_Type *spi, struct frdm_spi_mode *mode, uint32_t hz) {

        if(mode->frame < FRDM_SPI_MIN_FRAME_SIZE) {
          return -1;
        }

        // Enable clock
        SIM_SCGC6 |= SIM_SCGC6_SPI0(FRDM_ENABLE);

        // For debug purpose
        SPI_MCR_REG(spi) &= ~SPI_MCR_CONT_SCKE_MASK;
        SPI_MCR_REG(spi) |= (FRDM_ENABLE<<SPI_MCR_CLR_RXF_SHIFT);

        // Master/slave

        SPI_MCR_REG(spi) &= ~SPI_MCR_MSTR_MASK;
        SPI_MCR_REG(spi) |= (mode->mode<<SPI_MCR_MSTR_SHIFT);

        if(mode->mode == FRDM_SPI_MASTER) {
          //Frame size
          SPI_CTAR_REG(spi,0) &= ~SPI_CTAR_FMSZ_MASK;
          SPI_CTAR_REG(spi,0) |= (((mode->frame-1) & 0x0F)<<SPI_CTAR_FMSZ_SHIFT);

          // Spi mode
          SPI_CTAR_REG(spi,0) &= ~SPI_CTAR_CPOL_MASK;
          SPI_CTAR_REG(spi,0) |= (mode->CPOL)<<SPI_CTAR_CPOL_SHIFT;
          SPI_CTAR_REG(spi,0) &= ~SPI_CTAR_CPHA_MASK;
          SPI_CTAR_REG(spi,0) |= (mode->CPHA)<<SPI_CTAR_CPHA_SHIFT;

          //Always in msb mode

          SPI_CTAR_REG(spi,0) &= ~SPI_CTAR_LSBFE_MASK;

        } else if(mode->mode == FRDM_SPI_SLAVE) {
          /*TODO*/
        }

        //frequency
        SPI_CTAR_REG(spi,0) &= ~SPI_CTAR_ASC_MASK;
        SPI_CTAR_REG(spi,0) |= 1<<SPI_CTAR_ASC_SHIFT;
        SPI_CTAR_REG(spi,0) &= ~SPI_CTAR_PASC_MASK;        SPI_CTAR_REG(spi,0) |= 0<<SPI_CTAR_PASC_SHIFT;

        SPI_CTAR_REG(spi,0) &= ~SPI_CTAR_DBR_MASK;
        SPI_CTAR_REG(spi,0) |= 0<<SPI_CTAR_DBR_SHIFT;

        // Fifo
        SPI_MCR_REG(spi) &= ~SPI_MCR_DIS_TXF_MASK;
        SPI_MCR_REG(spi) |= 0<<SPI_MCR_DIS_TXF_SHIFT;

        //Enable
        SPI_MCR_REG(spi) &= ~SPI_MCR_MDIS_MASK;
        SPI_MCR_REG(spi) |= 0<<SPI_MCR_MDIS_SHIFT;



        // Start hardware
        SPI_MCR_REG(spi) &= ~SPI_MCR_HALT_MASK;
        SPI_MCR_REG(spi) |= 0<<SPI_MCR_HALT_SHIFT;

        return 0;

}

[Sissors]

Waarschijnlijk krijg je meer feedback in het EL forum, dit is niet zozeer een 'hoe te programmeren', maar meer 'hoe werkt het device'.

Om te beginnen: Zet je de pinout ergens anders goed, of is dat het stuk dat mist?

[NMe]

^^ dat inderdaad.

>> Elektronica

[DaWaN]

Lees de reference manual van de Kinetis even door (http://cache.nxp.com/file...umentation&fileExt=.pdf):

50.4.5 Continuous Serial Communications Clock
The module provides the option of generating a Continuous SCK signal for slave
peripherals that require a continuous clock.
Continuous SCK is enabled by setting the CONT_SCKE bit in the MCR. Enabling this
bit generates the Continuous SCK regardless of the MCR[HALT] bit status. Continuous
SCK is valid in all configurations.
Continuous SCK is only supported for CPHA=1. Clearing CPHA is ignored if the
CONT_SCKE bit is set. Continuous SCK is supported for Modified Transfer Format.
Clock and transfer attributes for the Continuous SCK mode are set according to the
following rules:
• When the module is in SPI configuration, CTAR0 is used initially. At the start of
each SPI frame transfer, the CTAR specified by the CTAS for the frame is used.
• In all configurations, the currently selected CTAR remains in use until the start of a
frame with a different CTAR specified, or the Continuous SCK mode is terminated.
It is recommended to keep the baud rate the same while using the Continuous SCK.
Switching clock polarity between frames while using Continuous SCK can cause errors
in the transfer. Continuous SCK operation is not guaranteed if the module is put into the
External Stop mode or Module Disable mode.
Enabling Continuous SCK disables the PCS to SCK delay and the Delay after Transfer
(tDT) is fixed to one SCK cycle. The following figure is the timing diagram for
Continuous SCK format with Continuous Selection disabled.
NOTE
In Continuous SCK mode, for the SPI transfer CTAR0 should
always be used, and the TX FIFO must be cleared using the
MCR[CLR_TXF] field before initiating transfer.

Waarschijnlijk voldoe je niet aan één van de bovenstaande voorwaarde(n).
Aangezien je de continous clock mode in de meeste gevallen niet nodig hebt zou ik de SPI op een normale manier gebruiken; ik zie geen enkele meerwaarde in het enablen van de continous clock mode voor testdoeleinden.