General Details Name Crusoe
Codenames TM3200 (formerly known as TM3120)
TM5400
TM5600
Family/Generation Dynamic Translation
Vendor Transmeta
Manufacturer IBM
First Introduction Jan 19, 2000 (TM3200 and TM5400)
Oct 7, 2000 (TM5600)
Physical Details Package Type 474 Pin BGA
Package Size 3.25 cm x 2.50 cm
Socket or Slot Proprietary
Transistors ??? (TM3200, includes 96 KB L1, 8 KB LPM, 4 KB LDM)
??? (TM5400, includes 128 L1, 256 KB L2, 8 KB LPM, 8 KB LDM)
36.8M (TM5600, includes 128 L1, 512 KB L2, 8 KB LPM, 8 KB LDM)
Process Technology 0.22 µm, CMOS (TM3200)
0.18 µm, CMOS (TM5x00)
Die Size 77 mm² (0.22 µm TM3200)
73 mm² (0.18 µm TM5400)
88 mm² (0.18 µm TM5600)
Electrical Details Split Voltage Yes
Core Voltage 1.5 V (TM3200)
1.2..1.6 V (TM5x00 with LongRun Technology)
L2 Voltage N/A (TM3200)
1.2..1.6 V (TM5x00 with LongRun Technology)
I/O Voltage 3.3 V (SDR SDRAM)
2.5 V (DDR SDRAM, TM5x00 only)
3.3 V (PCI)
Typical Power 1-3 W
Maximum Power ??? W
Cooling Not Required
Clock Frequencies CPU Core Speed 333, 366, 400 MHz (TM3200)
500..700 MHz (TM5400 with LongRun Technology)
300..600 MHz (TM5600 with LongRun Technology)
L1 Cache Speed 1.0x Core Speed
L2 Cache Speed N/A (TM3200)
1.0x Core Speed (TM5x00)
External Bus Speed 66..133 MHz SDR SDRAM
100..133 MHz DDR SDRAM (TM5x00 only)
33 MHz PCI
Core/Bus Ratio 2.0x, 3.0x, 4.0x, 5.0x, ... 15.0x (SDRAM)
Miscellaneous usual Motherboard Single Processor Mobile Platform
usual Chipset Integrated North Bridge (Memory and PCI Controller)
Pictures TM3200 Top (7 KB JPG)
TM3200 Die (184 KB JPG)
TM5400 Top (9 KB JPG)
TM5400 Die (227 KB JPG)
TM5400 Block Diagram (50 KB JPG)
Processor Core Generic Details VLIW, In-order Execution, Dynamic Translation
Specific Details 64 and 128 Bit VLIW Molecules
Commit/Rollback Architecture
Code Morphing Software (CMS)
Registers 32 Bit Integer, 80 Bit FP, 64 Bit MM
64x/48x (Primary/Shadowed) 32 Bit General Purpose Registers
32x/16x (Primary/Shadowed) 80 Bit FP General Registers
Pipeline Depth 7 (Integer), 10 (FP)
Instruction Decoder Code morphing Software (CMS)
Interprets and/or Translates x86 Code into VLIW Code
Execution Units 2x ALU, 1x Load/Store, 1x Branch, 1x FP/MM
Execution Speed 1x VLIW Molecule/Cycle
up to 4x Atoms/Molecule
Processor Buses Address Bus Width 32 Bit
Data Bus Width 64 Bit (SDR SDRAM)
64 Bit (DDR SDRAM, TM5x00 only)
32 Bit (PCI)
Physical Memory 2^32 Bit = 4 GB
Virtual Memory (8,190 + 8,192) x 4 GB = 65,528 GB (~64 TB)
Multiprocessing N/A
Power Management HLT, STPCLK, SMI/SMM, Quick Start, Deep Sleep
LongRun Technology (TM5x00)
Processor Caches Level 0 N/A
Level 1 Code 64 KB, 8-Way, 64 Bytes/Line
8 KB Local Program Memory (LPM)
Data 32 KB, 8-Way, 32 Bytes/Line (TM3200)
4 KB Local Data Memory (LDM) (TM3200)
64 KB, 16-Way, 32 Bytes/Line (TM5x00)
8 KB Local Data Memory (LDM) (TM5x00)
Level 2 Unified N/A (TM3200)
256 KB, 4-Way, 128 Bytes/Line (TM5400)
512 KB, 4-Way, 128 Bytes/Line (TM5600)
Level 3 Translation Cache 8..16 MB
Processor Buffers Buffers Alias Hardware
Gated Store Buffer
16x 32 Bit CPU-to-PCI Write Buffer
16x 32 Bit PCI-to-DRAM Write Buffer
16x 32 Bit DRAM-to-PCI Read Buffer
Prefetch Queue N/A
Branch Prediction Yes
TLB 256 Entries, 4-Way
T-Bit Buffer
Instruction Set Regular IA-32
Floating Point Integrated
Multi Media MMX
Processor Modes Real, Protected, Virtual, Paging, SMM
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