Wat jij hierboven schetst had ik ook als idee. En om dat gezeur te voorkomen heb ik dus gekozen voor een plank met onboard VGA. Volgens Intel kan in het PCI-e X16 slot elke PCI-e kaart werken.
Zit nu lekker te lezen op de Intel site en nu zie ik dit in de chipset PDF:
1.3.4 PCI Express* Interface (Intel® 82Q965, 82G965, 82P965
(G)MCH Only)
The (G)MCH contains one 16-lane (x16) PCI Express port intended for an external PCI
Express graphics card. The PCI Express port is compliant to the PCI Express* Base
Specification revision 1.1. The x16 port operates at a frequency of 2.5 Gb/s on each
lane while employing 8b/10b encoding; the port supports a maximum theoretical
bandwidth of 40 Gb/s in each direction. The 82Q965 and 82G965 GMCHs multiplex the
PCI Express interface with the Intel® SDVO ports.
• One, 16-lane PCI Express port intended for graphics attach, compatible to the PCI
Express* Base Specification revision 1.1a.
• PCI Express frequency of 1.25 GHz resulting in 2.5 Gb/s each direction
• Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per pair of
250 MB/s given the 8b/10b encoding used to transmit data across this interface
• Maximum theoretical realized bandwidth on the interface of 4 GB/s in each
direction simultaneously, for an aggregate of 8 GB/s when x16.
• PCI Express* Graphics Extended Configuration Space. The first 256 bytes of
configuration space alias directly to the PCI Compatibility configuration space. The
remaining portion of the fixed 4-KB block of memory-mapped space above that
(starting at 100h) is known as extended configuration space.
Introduction
30 Datasheet
• PCI Express Enhanced Addressing Mechanism. Accessing the device configuration
space in a flat memory mapped fashion.
• Automatic discovery, negotiation, and training of link out of reset
• Supports traditional PCI style traffic (asynchronous snooped, PCI ordering)
• Supports traditional AGP style traffic (asynchronous non-snooped, PCI Expressrelaxed
ordering)
• Hierarchical PCI-compliant configuration mechanism for downstream devices (i.e.,
normal PCI 2.3 Configuration space as a PCI-to-PCI bridge)
• Supports “static” lane numbering reversal. This method of lane reversal is
controlled by a Hardware Reset strap, and reverses both the receivers and
transmitters for all lanes (e.g., TX[15]->TX[0], RX[15]->RX[0]). This method is
transparent to all external devices and is different than lane reversal as defined in
the PCI Express Specification. In particular, link initialization is not affected by
static lane reversal.
Ook lekker, de specificaties van de PCI-e 1.1 architectuur mag je alleen downloaden met username en password???
http://www.pcisig.com/specifications/pciexpress/base